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An approximate estimate of the output resistance of the buffer may be obtained from (44,45,126) RO ≈ L/W µCox (VDD − VT ) (14) where Ȑ is the channel mobility, VDD is the power supply voltage, and VT is the device threshold voltage. Equation (14) is derived from the large signal I–V equation of a MOSFET operating in the saturation region close to the linear region and is accurate for small channel geometries because velocity saturation decreases the quadratic behavior of the MOS device operating in the saturation region.

Because the data flow is nonrecursive, fewer pipeline registers are required as compared to those structures that contain substantial feedback. Furthermore, the multiplier tends to be the critical element (in terms of speed, area, and power) in most DSP circuits. Heavily pipelined multipliers requiring sophisticated clock distribution networks are the focus of considerable research. In this subsection, specific examples of clock distribution networks in highly pipelined DSP-based multipliers implemented in VLSI technologies are described.

As long as this horizontal clock skew is less than the local data path delay between cells, no negative clock skew condition will occur [see the subsection entitled ‘‘Minimum Data Path/Clock Skew Constraint Relationship’’ and Eq. (6)], and the multiplier array will operate properly. Furthermore, additional cells can be added to the array without creating any race conditions as long as the same constraint is maintained. E B C F A 8 Bit ؋ 8 Bit Pipelined Multiplier (11,56,143–146) D Clock path Figure 23.

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64.VLSI Systems by John G. Webster (Editor)

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